1. Field of the Invention
This invention relates generally to bipolar memory cells and, more particularly, to a bipolar memory cell having an improved diode load element.
2. Background Art
Bipolar memory cells are circuits wherein information may be stored in a low current stand-by mode and may be written into or read from in a higher current mode.
Some bipolar memory cells comprise a pair of cross-coupled multi-emitter transistors operating as a latch. The bases of the transistors are cross-coupled to each others collector. A first emitter of each transistor is coupled to a stand-by current drain line. A second emitter of one transistor is connected to a first bit line and a second emitter of the second transistor is connected to a second bit line. The collectors are further coupled to a row or column select line by a load.
The load implements the non-linear resistance required to maintain reasonable cell differential voltage under both the low current stand-by mode and the higher current read/write mode. Cell differential voltage is designed at typically between 350 and 700 millivolts during stand-by and provides sufficient noise immunity.
One previously known load arrangement comprises a PN diode in parallel with a resistor. The diode decreases the possibility of the transistors from going into heavy saturation. The read/write mode requires an increased current of 30 to 50 times that of the stand-by mode. In the stand-by mode, the differential voltage is low enough so that the diode is not turned on. In the read/write mode, the increased current goes through the diode instead of the resistor. Therefore, a higher current exists across the combination cell load elements for only a small increase in differential voltage. Typically, for one decade of additional current, an increase of only about 65 millivolts is obtained once the clamp diode is turned on.
Another previously known load arrangement comprises a PNP transistor as the load. First and second PNP transistors have their emitters connected to the select line. A collector of the first PNP transistor is connected to the base of the first multi-emitter transistor, the base of the second PNP transistor, and the collector of the second multi-emitter transistor. The base of the first PNP transistor is connected to the collector of the first multi-emitter transistor, the collector of the second PNP transistor, and the base of the second multi-emitter transistor. The second PNP transistor is similarly connected. A different version of this load arrangement has a first and second resistor coupled between the emitter and collector of the first and second PNP transistors, respectively.
Yet another previously known load arrangement comprises a diode formed in polysilicon. Such a diode has a slope factor, or diode ideality factor, of approximately two and results in a differential voltage greater than 200 millivolts, thereby producing a stable cell. This differential voltage can be retained over a wide current range so that the cell can still retain data at a very low current for power down operation.
Still another previously known load arrangement comprises a first PNP transistor having an emitter coupled to the select line, and a collector connected to the base of the first multi-emitter transistor. A second PNP transistor has an emitter connected to the select line and a collector connected to the base of the second multi-emitter transistor A third PNP transistor has an emitter coupled to the select line and a collector connected to the collector of the first multi-emitter transistor and the bases of both the first and third PNP transistors. A fourth PNP transistor has an emitter coupled to the select line and a collector connected to the collector of the second multi-emitter transistor and both the basis of the second and fourth PNP transistors.
All of the above previously known load arrangements have certain characteristics wherein it may be advantageous to use one instead of the other. However, all of these previously known load arrangements have a fundamental charge storage problem in the vertical PNP base region associated with the clamping diode of a resistor loaded cell and the injector of a PNP load cell. This charge storage results in long write pulse width and long write recovery times for these cells. In order to turn the cell off, the holes that have been injected into the epitaxial (epi) region, or collector of the multi-emitter transistor, must be removed and supplied to the side of the cell that is turning on.
This charge storage problem may be reduced by using a Schottky diode in place of the PN diode of the above mentioned load arrangement comprising a PN diode in parallel with a resistor. However, a Schottky diode loaded cell is disturb sensitive. The cell is subject to an accidental change of state, particularly at high temperatures.
Thus, what is needed is a memory cell having faster write pulse width and write recovery times by reducing the charge stored in the load epi region while avoiding the inherent disturb sensitivity of the Schottky diode loaded cell.